Instruction Cache Compression for Embedded Systems

Code compression could lead to less overall system die area and therefore less cost. This is significant in the embedded system field where cost is very sensitive. In most of the recent approaches for code compression, only instruction ROM is compressed. Decompression is done between the cache and memory, and instruction cache is kept uncompressed. Additional saving could be achieved if the decompression unit is moved to between CPU and cache, and keep the instruction cache compressed as well. In this project we explored the issues for compressing the instruction cache. In the process, we constructed a high level implementation for a 64-bit, 5-stage pipeline MIPS like processor with compressed instruction cache. We developed a compression algorithm with instruction level random access within the compressed file. In addition we devised a branch compensation cache, a small cache mechanism to alleviate the unique branching penalties that branch prediction cannot reduce.